Better converter efficiency with eGaN FETs

by Alex Lidow and David Reusch, Efficient Power Conversion Corp.

Gallium-nitride FET technology has improved markedly in the past five years. Power converters based on GaN FETs are living up to the promise of low power losses at an economical price.

Enhancement-mode gallium-nitride (eGaN) FETs can switch at speeds ten times faster than the best available silicon transistors. This speed advantage is the reason GaN transistors can boost power conversion efficiency and enable new, exciting applications that are simply beyond the reach of the venerable silicon power MOSFET.No wonder, then, that GaN power semiconductors are showing up in an expanding array of efficient power conversion applications. The technology is rapidly developing and product experience in the field is expanding.

GaN devices, grown on a low-cost silicon substrate, include high electron mobility transistors (HEMT) that significantly outperform the aging silicon MOSFET. Material benefits of GaN include a higher critical electric field strength, which allows the device terminals to be pulled closer together, and higher electron mobility, allowing the electrons to move with less friction between these shortened terminal connections. The improved electrical and thermal performance qualities of chip-scale-packaged eGaN FETs and ICs enable new levels of in-circuit performance, raising the bar for power conversion efficiency and economics.

eGaN FETs operate a lot like silicon power MOSFETs, but they have a few fundamental differences that require attention during circuit designs. The most important difference between them is that eGaN gate voltage is limited to a maximum of 6 V. To maximize eGaN FET performance, it’s best to drive the devices between 4 to 5 V. The lower maximum gate voltage makes it advisable to employ gate drive circuitry that can regulate the voltage to ensure safe operation and to minimize the parasitic inductance of the gate drive loop. In collaboration with Texas Instruments, a series of drivers have been developed to bring simplicity and reliability to meeting the challenges of driving eGaN FETs. This family of drivers allows designers to easily adopt eGaN FETs for use in most applications.

Beyond the introduction of GaN-specific gate drivers, the reliability of eGaN FETs has significantly improved since their introduction in 2009. Looking at gate reliability, there are several mechanisms that can contribute to failure in the field. A common means to measure reliability is to apply High Temperature Gate Bias (HTGB) stress at high gate voltage. These failure mechanisms include dielectric failure, gate sidewall rupture and a rise in off-state drain leakage resulting from gate stress.

To determine the voltage acceleration of HTGB failure, technicians conducted a matrix of tests between 6 and 7 V, all at 150° C. Note that this voltage range is outside the safe operating range of less than 6 V for eGaN FETs. The time-to-failure is determined from periodic parametric monitoring of the parts every two minutes. The failure criterion is a rise in the off-state drain or gate leakage beyond data sheet limits.

Dead-Time and parasitics
As designers continue to boost frequency in power conversion, dead-time management becomes a critical factor in getting high efficiency and good regulation. For eGaN FETs with a higher forward “diode” drop, this is especially true. The “body diode” mechanism is both better and worse than that of a silicon MOSFET. An examination of the drain-source current flowing through the “body diode” as a function of the source-to-drain voltage at both room temperature and 125° C shows the eGaN FET has a significantly higher forward drop than the Si MOSFET. In low-voltage applications where the diode conduction period is large, an external Schottky diode has been shown to significantly improve GaN performance.

An offsetting advantage of the eGaN FET “body diode” mechanism, especially at higher frequencies, is that there is no recovered charge, Qrr. The eGaN FET turns off immediately when the voltage is removed from drain-to-source. In a silicon MOSFET, it takes several nanoseconds for all the charge to sweep out of the device, and the reverse recovery charge is a major high-frequency loss component.

Parasitic inductances make converters less efficient and generate unwanted voltage stresses. As GaN power devices continue to switch at higher speeds, the reduction of parasitic inductances must keep pace or designers will have to tradeoff switching speed for lower voltage stresses, sacrificing performance for reliable operation.

Traditionally, the major source of parasitics in a power device has been the device package. A conventional packaging technique for a vertical power MOSFET involves connecting the drain to the printed circuit board, generally with a large pad. The drain pad has a die-attach material that is used to connect the drain pad to the drain of the vertical MOSFET die. On the opposite side of the MOSFET are die-attach materials for the source and gate connections. Lastly, the source and gate connections have clips to allow connection to the circuit board. Each of these packaging steps adds resistance, inductance, size, thermal impedance and cost to the power device.

An advantage of high-voltage lateral eGaN FET transistors is that all the electrical connections reside on the same side of the die, eliminating the need for complex, high-parasitic two-sided packaging common to MOSFETs. With eGaN FET chip-scale land grid array (LGA) packages, the eGaN FET mounts directly to the PCB with drain, source and gate connections. This simple packaging technique reduces the resistance, inductance, size, thermal impedance and cost of the power device.

With the lower package parasitics inherent in eGaN FET chip-scale format, the printed circuit board (PCB) layout can become the limiting factor in converter performance. To minimize the common- source inductance added by PCB layout, the gate driver loop and high-frequency power loop should be located where they have little interaction.

Keeping these loops away from each other minimizes the common source inductance to the ultra-low internal eGaN FET package inductance. To reduce the high-frequency power-loop inductance contributed by the PCB, we’ve developed an optimal layout that uses the first inner layer as a high-frequency power-loop return path. Located between the two eGaN FETs is a series of vias, used to connect the top layer to the inner layer return path, arranged to match the land grid array fingers of the synchronous rectifier (SR). This return path sits directly underneath the top layer’s power loop path, minimizing the physical loop size and providing magnetic field self-cancellation.

A side view of the optimal layout illustrates the concept of creating a low-profile magnetic field self-canceling loop in a multilayer PCB structure. Additional source vias are used on the lower side of the bottom transistor (SR) to further reduce low-frequency resistance and thermal resistance.

Paralleling eGaN FETs
The concept of paralleling devices is simple; the designer can use multiple smaller devices that appear and operate as a single, larger device. The on-resistance drops and the capacitances rise in proportion to the number of devices paralleled. In practice, as parasitic imbalance rises between the parallel devices, their ability to parallel worsens, limiting current-handling capability. Researchers have shown that parasitics must be both minimized and balanced for ultra-fast eGaN FETs operating in parallel to ensure good dynamic current sharing.

We present two designs in the interest of evaluating traditional paralleling layouts and proposing an improved parallel layout. In the first design, four GaN transistors sit in close proximity to operate as a “single” power device, with a single high-frequency power loop. The drawbacks of this layout are larger parasitic inductances and greater parasitic imbalance between the parallel devices, leading to current sharing and thermal issues.

The second design uses four distributed power loops, located symmetrically around a single gate driver. The design will provide the lowest overall parasitics for each device pair and most importantly, provide the best balancing of the parasitic elements, ensuring proper parallel operation.

A thermal imbalance is evident in the conventional paralleling design, where a hot spot develops on the devices handling a greater portion of the power as a result of parasitic inductance imbalance. The top switch closest to the input capacitors, T1, has a maximum temperature more than 10° C higher than the top switch furthest away from the input capacitors, T4.

For the proposed distributed power loop design, there is a good thermal balance and negligible difference in temperature between the devices. There is also a good distribution of the heat by distributing the higher-loss top devices on the PCB and not clustering them together.

For an example of the progress seen with GaN transistors in a short period of time, consider the application of eGaN FETs in 12 Vin POL converters. Five years ago, the performance of GaN transistors suffered from an insufficient understanding of the nuances involved with this new technology. New technological breakthroughs, such as monolithic integration, let GaN transistors again raise the bar for high-frequency power conversion performance.

References

Efficient Power Conversion Corp.
epc-co.com

Texas Instruments
“Overview for GaN Solutions”
www.ti.com/gan

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M. A. de Rooij. Wireless Power Handbook: A Supplement to GaN Transistors for Efficient Power Conversion, First Edition, Power Conversion Publications, 2015.

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