It can be difficult to correct for power factor in converters that have different conduction modes. A special technique can make corrections smoothly.
By Joel Steenis, Alex Dumais, MICROCHIP TECHNOLOGY, INC.
DESIGNERS of power factor correction (PFC) circuits will invariably notice distortion as the input current approaches zero. The distortion problem becomes progressively worse at light loads. It arises because of the two fundamental operating modes of a power converter and because the current measurement signals are below the noise floor.
The two operating modes of a converter are continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The distinction between the two operating modes is made based on inductor current. In CCM the inductor current is a triangle-shaped waveform. In DCM the inductor current waveform is triangular shaped but has “flat spots” at zero current.
A technique called bumpless control addresses the issue of alternating between CCM and DCM, is practical to implement, and reduces total harmonic distortion (THD) in hardware.
The boost converter is a common building block for a number of PFC topologies and has different small-signal characteristics for each operating mode. Small-signal models GiCCM(S) and GiDCM(S) for CCM and DCM respectively in each operating mode are:
where R is the load resistance, C is the output capacitance, L is the boost inductance, M is the voltage conversion ratio (VOUT/VIN), Ts is the switching period, D1 is the duty cycle of the converter in DCM, D′ is the complement of the duty cycle (D′ = 1-D) in CCM, VOUT is the output voltage, VIN is the input voltage, îL is the small-signal variation in inductor current, d is the small signal variation in duty cycle, and s is the frequency in rad/sec.
An examination of the Bode plot for a representative system makes it clear that a single controller will yield quite different loop gains and result in different responses for each operating mode. A qualitative comparison of the two plant qualities shows that a controller designed for a PFC operating in CCM will result in a low-bandwidth loop when operating in DCM.
To address the CCM/DCM issue, one may instinctively choose to use two controllers. In principle, this approach is valid; however, it will invariably lead to a discontinuity when switching between controllers. To resolve the discrepancy in controller outputs, i.e. controller “bump,” the controller structure must be modified.
One approach is to add a sub-controller to each controller in the original configuration. Also added are complementary switches which control each sub-controller, making it active or inactive. The switches are additionally configured to force the output of the inactive controller to track the output of the active controller.
Readers will note a potential source of confusion: There are controllers in the controller. The concept of “the controller” becomes ambiguous and notation is of utmost importance. For clarity, we introduce the term “master controller.” This is the controller with input and output always connected to the system. The “master controller” may contain any number of sub-controllers and switches, connected in a variety of ways.
Simply put, the bumpless controller switches between sub-controllers, each with their own feedback loop. The sub-controllers are designed to track either the input to the bumpless controller or the output of the bumpless controller depending on the position of two switches, SCCM and SDCM. The switches control which sub-controller is active or inactive and force the output of the inactive controller to track the output of the active controller.
Consider two cases that refer to the accompanying figures.
CASE 1: SWITCH SDCM IS CLOSED AND SCCM IS OPEN
In the case of a DCM controller, the signal “eDCM bump” is zero. The bump removal loop is inactive for the DCM controller, and the DCM controller operates normally.
In the case of a CCM controller, the signal “eCCM bump” is the difference between the output of the CCM controller and DCM controller. The bump removal controller is active for the CCM controller. (It should be forcing the output of the CCM controller to track the output of the DCM controller.)
The CCM controller does not operate normally. The output of the DCM controller is now the input for the CCM controller, and the input to the bumpless controller acts as a disturbance.
CASE 2: SWITCH SCCM IS CLOSED AND SDCM IS OPEN
In the case of a CCM controller, the signal “eCCM bump” is zero. The bump removal loop is inactive for the CCM controller, so the CCM controller operates normally.
In the case of a DCM controller, the signal “eDCM bump” is the difference between the output of the DCM controller and CCM controller. The bump removal controller is active for the DCM controller. (It should be forcing the output of the DCM controller to track the output of the CCM controller.)
The DCM controller does not operate normally. The output of the CCM controller is now the input for the DCM controller and the input to the bumpless controller acts as a disturbance.
To summarize, there are four feedback loops to be considered in the bumpless controller scheme: the plant/DCM controller loop, plant/CCM controller loop, DCM controller/KBUMP DCM loop, and the CCM controller/KBUMP CCM loop. The controllers for each of these loops may be synthesized using pole placement, K-factor, or other methods. The design objectives for the plant/DCM controller and plant/CCM controller loops are germane and addressed in many references.
Conversely, design objectives for the DCM controller/KBUMP DCM loop and the CCM controller/KBUMP CCM loop are opaque. Given the DCM and CCM controllers (sub-controller 1 and sub-controller 2), one must consider the output of either controller near the time of transition. Given the frequency and shape of the signal to be tracked, one may define a structure (PID, two pole/two zero, etc.) for KBUMP CCM and KBUMP DCM that will result in optimal performance for the given resources.
To see bumpless control in an actual application, consider the example of a 750-W semi-bridgeless PFC. The PFC is based on the Microchip dsPIC33EP64GS502 microcontroller and fits into a standard 1U form factor. It was designed to meet the CSCI (Climate Savers Computing Initiative) titanium efficiency spec.
Both the CCM and DCM controllers are type 2 and use constant-gain bump removal controllers. Computational complexity is always a concern when implementing advanced control algorithms. With the current control loops operating at 100 kHz, the bumpless controllers use 30 cycles more (4.3% more MIPS) than a single CCM controller.
One will note from the accompanying Bode plots for this example that the loop gain in DCM is lower than the loop gain in CCM. This is to guard against instability in the case of CCM/DCM detection issues, while still providing greater bandwidth then can be had from a CCM controller when the plant is in DCM.
The PFC was simulated using the SimPowerSystems toolbox in Matlab Simulink. The simulation predicted a THD of 16.5% at light loads when using a CCM controller and a THD of 8.9% at light loads when using a bumpless controller.
A review of performance specifications reveals that the bumpless controller reduces THD by approximately 2% at light loads. This is a marked improvement, given that little effort was devoted to tuning the controllers for optimal performance, and the CCM/DCM detection scheme detected the transition earlier than expected.
All in all, the absence of bumpless control leads to PFC circuits that have distortion as a result of two distinctly different operating modes. Simply switching between two controllers addresses the plant response in each mode but not the transition between the two modes. Adding the bumpless controller addresses the plant response in each operating mode as well as the transition. Bumpless controllers are practical to implement and reduce PFC THD in hardware.
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