When it comes to high-frequency transformer design, the careful management of parasitic elements is essential to ensure converter efficiency. Parasitic self-capacitance and leakage inductance matter when associated with switching losses, electromagnetic interference, and resonance issues in power electronics.
This article examines how specific turn progressions, ranging from U-Type to Serpentine and 3D-molded sector windings, impact the parasitic profile of magnetic components.
How does turn progression affect parasitic self-capacitance?
Parasitic self-capacitance refers to the electric field energy stored within the winding structure, governed by the equation E = CV2/2. Hence, self-capacitance depends on the voltage potential difference between adjacent conductors or layers. The winding scheme determines this potential distribution.
Architectures that place turns with large potential differences adjacent to one another result in higher stored electrostatic energy and effective capacitance. On the other hand, architectures that minimize the voltage gradient between adjacent turns or layers exhibit lower parasitic capacitance.
Regarding standard windings, how do U-Type and Z-Type architectures differ?
One of the key distinctions lies in standard non-interleaved winding methods. They manage the layer-to-layer transition differently, which means they exhibit distinct capacitive behaviors.
The U-Type progression, in Scheme A of Figure 1, consists of completing one full layer (e.g., turns 1–4) before starting the next layer immediately above the end of the previous layer (e.g., turn 5 sits above turn 4).
This configuration creates a high potential difference at the transition point, where the end of the first layer (high potential relative to the start) is physically adjacent to the start of the second layer. Such a move leads to a steep voltage gradient, resulting in higher stored electrostatic energy and higher self-capacitance compared to other standard schemes.
In the Z-Type progression, in Scheme B of Figure 1, the wire returns across the bobbin so that the second layer begins directly above the starting point of the first layer (e.g., turn 5 sits above turn 1).
This arrangement allows for a more consistent potential difference between adjacent layers. Additionally, simulations suggest that the energy density between layers is lower than in the U-type configuration, resulting in reduced self-capacitance.
Why are Sectioned and Bank windings used for low-capacitance applications?
Sectioned (Scheme C) and Bank (Scheme D) windings are often used to minimize capacitance by modifying the voltage gradient across the winding structure. As shown in Scheme D in Figure 1, this method uses a vertical, back-angled progression where turns are stacked upon previous turns immediately, rather than filling a horizontal layer first.
The point is that this architecture minimizes the voltage difference between physically adjacent turns. A closer look via FEA confirms that Scheme D stores less electrostatic energy between layers. For example, comparative studies show Bank winding can achieve measured self-capacitance as low as 1.3 pF, compared to 28 pF for standard U-Type windings.
Sectioned winding scheme divides the winding into physically separated sections (e.g., turns 1–2 are separated from 3–4 by a dielectric wall). Dividing the total winding voltage across separated sections reduces the effective voltage potential across any single section. In other words, this results in low self-capacitance (e.g., measured at 4.2 pF), making it effective for high-voltage applications.
What is the trade-off regarding leakage inductance in these schemes?
Though Schemes A, B, C, and D, when implemented as simple primary/secondary buildups, isolate the windings to manage capacitance, this physical separation increases the magnetostatic energy stored in the space between the windings. This constitutes leakage flux.
Therefore, non-interleaved designs typically exhibit higher leakage inductance. For example, a standard U-Type design (W1) might measure 550 nH of leakage inductance.
To reduce leakage inductance, engineers often use interleaved structures. Interleaving minimizes MMF peaks and improves magnetic coupling, reducing leakage inductance for the same purpose. However, the closer proximity of the windings generally causes inter-winding capacitance to increase.
How does the Serpentine method address this problem in high-frequency planar transformers?
Planar transformers in LLC resonant converters face challenges with parasitic capacitance due to the surface area of flat windings. The Interleaved Serpentine Winding method, shown in Figures 2(e) and (f), deals with this issue.
Unlike U-Type planar windings, where a full layer is completed before moving to the next, the Serpentine method employs a horizontal spiral structure that alternates vertically between the upper and lower layers.
- Capacitance reduction: Alternating layers (e.g., Turn 1 on bottom connects to Turn 2 on top) allow the potential difference between adjacent vertical turns to reduce to approximately V/n (where n is the number of turns).
- Inductance reduction: It is worth mentioning that experimental data indicate Serpentine windings can achieve lower leakage inductance (0.07 μH) compared to U-Type planar windings (0.54 μH) while simultaneously reducing the effective capacitance.
How do 3D-printed molds affect toroidal transformers?
Toroidal transformers present specific geometric challenges for optimization. Figure 3 illustrates research on 3D-printed Polylactic Acid (PLA) molds, demonstrating a method to simultaneously manage capacitance and inductance.
With the use of a PLA mold, this architecture covers the secondary winding, with the primary winding wound over the mold in a 180° sector configuration.
- Capacitance, where the mold provides a dielectric barrier and physical distance, reducing inter-winding parasitic capacitance by approximately 87% (to ~20 pF).
- Inductance, just like standard theory suggests, physical spacing typically increases leakage inductance. However, this modified design allows for an increase in the mean length turn of the primary winding. As a result, this geometric change leads to a measurable reduction in leakage inductance compared to the conventional design.
Summary
The progression of turns is an important design variable in transformer fabrication. Bank (Scheme D) and Sectioned (Scheme C) windings offer lower capacitance but may exhibit higher leakage inductance in non-interleaved setups. In planar applications, the Serpentine method effectively reduces both parameters. Additionally, for toroidal applications, 3D-printed molds enable sector-winding geometries that suppress both capacitance and leakage inductance so that high-frequency inverters can operate more efficiently.
References
High-Frequency Planar Transformer Based on Interleaved Serpentine Winding Method With Low Parasitic Capacitance for High-Current Input LLC Resonant Converter, IEEE Access
Investigation of Transformer Winding Architectures for High-Voltage (2.5 kV) Capacitor Charging and Discharging Applications, IEEE Transactions on Power Electronics
High Frequency Transformer’s Parasitic Capacitance Minimization for Photovoltaic (PV) High-Frequency Link-Based Medium Voltage (MV) Inverter, MDPI
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