Parasitic inductance is an often-overlooked factor in power electronics circuits. This FAQ examines how stray inductances in components and PCB layouts create voltage overshoots, electromagnetic interference, and efficiency losses in switching applications.
Parasitic inductance is an unintentional and unavoidable characteristic of all electronic parts and their connections that reduces how well power electronics circuits switch. This stray inductance, which comes from the leads of components, PCB traces, and internal wires, causes three main problems: voltage spikes, ringing, and higher switching losses. These issues can compromise circuit reliability, efficiency, and electromagnetic compatibility.
Where does parasitic inductance come from?
Every conductor, no matter how small, possesses some level of inductance. In a switching power converter, the primary sources of parasitic inductance are component packaging and PCB layout.
Component packaging
The internal lead frames and bond wires that connect the semiconductor die to the external pins contribute significantly to the inductance. For example, the MOSFET package on the left side of Figure 1 shows where parasitic inductance comes from in a MOSFET package, including bonding wires, lead frame inductances, and internal gate resistance.
This visualization shows how seemingly minor physical elements within the component package create the inductive pathways that impact switching performance. The bonding wires, typically only a few millimeters long, can contribute several nanohenries of inductance that bother at high switching frequencies.
PCB layout
The length and geometry of PCB traces, especially in the high-current switching loops, create inductive paths. Longer and thinner traces result in higher parasitic inductance. Beyond absolute inductance values, asymmetrical trace routing creates unbalanced parasitic inductances between parallel current paths. The PCB layout in Figure 2 shows parasitic inductance in a half-bridge switching power module that uses symmetrical routing to ensure even current distribution.
Understanding these parasitic inductance sources is necessary because their effects on switching performance can be severe. The combination of these inductances creates three primary performance degradation mechanisms that can compromise circuit reliability, efficiency, and electromagnetic compatibility.
Three primary performance issues
The primary impact of parasitic inductance is its opposition to changes in current. This is mathematically expressed by the formula V=L(di/dt), where a rapid change in current (di/dt) across an inductor (L) induces a voltage (V). In switching circuits that operate at high frequencies and fast switching speeds, this relationship is the root cause of major performance degradation.
Voltage overshoot: a threat to reliability
During the turn-off of a switching transistor, such as a MOSFET, the current flowing through it is rapidly interrupted. This high di/dt across the parasitic inductance in the main power loop generates a voltage spike, or overshoot, across the switch. This overshoot voltage adds to the normal operating voltage and can exceed the transistor’s breakdown voltage rating, leading to device failure.
An experimental oscilloscope waveform in Figure 3 shows that there is a spike in voltage when switching happens in a power electronics circuit with uneven inductances. Loop 1 and Loop 2 show measurably different overshoot magnitudes, with Loop 2 exhibiting higher voltage spikes due to greater parasitic inductance in that current commutation path.
Ringing: an EMI nightmare
Following the initial voltage overshoot, the energy stored in the parasitic inductance resonates with the parasitic capacitance of the semiconductor device and the surrounding circuit. This creates a damped oscillation known as ringing. This high-frequency ringing is a major source of electromagnetic interference, which can disrupt the operation of nearby electronic systems. Furthermore, the voltage peaks during ringing can also stress the switching device.
Figure 4 shows an oscilloscope waveform demonstrating severe ringing in a SiC MOSFET inverter using traditional PCB design approaches. The oscillations in Vgate, Vload trans (drain-source voltage), Vload load, and Vdc clearly show the L-C resonance between parasitic inductances and junction capacitances that occurs when proper parasitic inductance management is not implemented.
The practical implications extend beyond just waveform quality. These oscillations create substantial EMI issues, which can stress devices beyond their ratings and can lead to system instability.
Increased switching losses
Parasitic inductance contributes to increased switching losses primarily through slower switching transitions. The common source inductance, which is shared by the gate drive loop and the main power loop, creates a negative feedback effect.
As the drain current changes rapidly during switching, a voltage is induced across the common source inductance that opposes the gate drive voltage. This slows down the turn-on and turn-off times of the transistor, leading to a longer period where both high voltage and high current are present, thus increasing switching losses.
Experimental data in Figure 5 demonstrates how source inductance (Ls) directly impacts switching efficiency. Part A shows the reduction in switching di/dt rates as Ls increases, while Part B quantifies the corresponding increase in both turn-on and turn-off switching losses.
Summary
Parasitic inductances should not be treated casually, as they still possess problems such as voltage overshoot, ringing, and switching losses. Even though the magnitude of the parasitic inductance appears very small, continued use for a longer period of time can reduce the reliability of power electronics circuits. It is advised that engineers continue to focus on basics such as packaging and PCB routing to reduce the impact of parasitic inductances. However, parasitic inductances are here to stay, at least for the near future.
References
Design of Half-Bridge Switching Power Module Based on Parallel-Connected SiC MOSFETs for LLC Resonant Converter with Symmetrical Structure and Low Parasitic Inductance, Electronics, MDPI
An Improved Investigation into the Effects of the Temperature-Dependent Parasitic Elements on the Losses of SiC MOSFETs, Applied Science, MDPI
Influence of driving and parasitic parameters on the switching behaviors of the SiC MOSFET, Frontiers in Energy Research
Realization of 1200 V, 50 A SiC MOSFET Inverter for Permanent Magnet Synchronous Motor, ResearchGate
Investigation, Evaluation and Optimization of Stray Inductance in Laminated Busbar, ResearchGate
Controlling Primary-Side Ringing, Monolithic Power Systems
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