GaN HEMTs are very reliable, but the precise answer is still being refined. Reliability relates to anticipated useful life and is typically measured in mean-time-to-failure. Reliability can be anticipated and determined in advance by testing and measurement. Proving and improving device reliability is an ongoing process. It begins with a device under test (DUT) being stressed until it fails, that’s followed by identifying the failure mechanism(s), developing cause and effect models, and improving subsequent device designs or fabrication processes, hopefully with higher reliability.
Gallium nitride (GaN) is a well-established but still evolving power conversion technology. GaN operation and physics are inherently different from silicon (Si). That means that new ways need to be developed to determine GaN reliability. This FAQ looks at some industry guidelines and standards for GaN reliability evaluation, considers the impact of early life failure testing on reliability predictions, and closes with a brief look at how several GaN makers are testing beyond the requirements of industry standards.
JEDEC and AEC-Q101 provide a starting point for delving into GaN reliability. The JEDEC JC-70.1 committee is focused on “GaN power electronic conversion semiconductor standards”, and has issued two ‘guidelines’ for evaluating GaN reliability (for more details on JEDEC standards for testing GaN, see: “Is Double-Pulse Testing Inadequate for GaN?”):
JEP180.01 – Provides a “guideline for switching reliability evaluation procedures for gallium nitride power conversion devices.” It includes guidelines for evaluating the switching reliability of GaN power HEMTs and assuring their reliable use in power conversion applications. It is generally applicable to planar enhancement-mode, depletion-mode, GaN integrated power solutions, and cascode GaN power switches.
JEP186 – Presents a “guideline to specify a transient off-state withstand voltage robustness indicator in datasheets for lateral GaN power conversion devices.” JEP186 describes different techniques that can be used. It does not establish preferences for any of the specification types presented, nor does the guideline address formatting of datasheets. It also doesn’t require that the datasheet parameters are used in production tests nor specify how the values were obtained; it’s really just a generic ‘guideline.’
Compared with the JEDEC guidelines, AEC-Q101 is a comprehensive testing standard. It details everything designers need to know to achieve compliance ranging from sample size requirements to detailed testing requirements and qualification requirements.
Examples of testing included in AEC-Q100 are high-temperature reverse bias (HTRB), high humidity, high-temperature reverse bias (H3TRB), high-temperature gate bias (HTGB), and highly accelerated stress testing (HAST). Rather than starting over, several GaN makers have used ACE-Q100 and other industry-standard tests and modified them to suit the unique characteristics of GaN devices better.
GaN devices are typically lateral structures compared to vertical Si devices. When a GaN HEMP is ON, current flows laterally from source to drain. The gate, source, and drain terminals are all on top of the devices. Unlike Si MOSFETs, GaN HEMTs have no oxide dielectric in the gate structure or p-n drain to source junction. The lateral structure of the GaN device increases possible sensitivity to humidity compared with Si MOSFETs.
It’s not just the structure; device physics are different for GaN and Si. In a GaN HEMT, a thin high-density layer of electrons called a 2-dimensional gas (2DEG) forms between the GaN and AlGaN layers (Figure 1). When an enhancement-mode GaN HEMT is unbiased (OFF), the 2DEG layer is broken beneath the gate, preventing current flow. A sufficiently high positive gate to source voltage generates a vertical field beneath the gate, reforming the 2DEG, completing the circuit between the drain and source, and turning the device ON.
The numerous structural and device physics differences between Si and GaN devices need to be considered by modifying a Si qualification plan for GaN devices. Some of the most important failure mechanisms to consider in GaN devices are charge trapping, hot-carrier degradation, and time dependent breakdown (TDB). TDB and hot-carrier degradation also occur in Si devices. TDB occurs in dielectrics due to high electric fields and causes increased leakage currents that can lead to hard failures. It’s considered in JEDEC JEP122H “Failure Mechanisms and Models for Semiconductor Devices.”
Hot-carrier degradation occurs in both Si MOSFETs and GaN devices. Hard switching can create hot carriers in Si MOSFETS and can generate defects. In GaN devices, both wear out and charge trapping can be caused by hot carrier degradation.
In a GaN HEMT, trapped electrons repel the electrons in the 2DEG channel, reducing the available electrons in the channel and increasing on resistance (RON) (Figure 2). Electrons can be trapped in the dielectrics, buffer layers, and interfaces. Trapping is caused by high drain voltages when the device is off or by hot electrons when the device is switching. The combined effect of the device’s normal RON plus the RON increase caused by charge trapping is called dynamic RON. It’s called dynamic since RON can recover as the trapped charge ‘detraps’ or dissipates. If the detrapping rate is low, there could be a greater impact from dynamic RON. Time scales similar to the switching time of the converter need to be used to evaluate the impact of dynamic RON.
Low duty cycles are best for validating the material quality and dynamic RON. The density of trapped electrons can increase as the device ages, contributing to higher RON. A device with a stable dynamic RON (minimal increase in the density of trapped electrons over time) is important to minimize conduction losses and reduce the possibility of premature failures.
Testing for dynamic RON is done by applying the maximum-rated DC VDS at the maximum-rated temperature. If there are no failures after 1,000 hours, the device is good. Applying DC VDS at maximum temperature, the available electrons come from the drain-source leakage current, IDSS. To accelerate trapping, voltages above the rated maximum are required. By using the hard switching circuit included in JEDEC JEP17, orders of magnitude more potential trapping electrons can be generated, independent of temperature (Figure 3).
The ‘bathtub curve’ represents the three phases in a product’s reliability. It starts with an infant mortality or early life failure (ELF) phase with relatively large numbers of failures with a decreasing frequency (Figure 4). Understanding the ELF phase is particularly important when designing burn-in processes to weed out the infant mortality and drive the remaining population to the bottom of the curve. ELF testing is also used in identifying important device failure mechanisms. JEDEC JESD47K includes early life failure (ELF) testing. The previously discussed JEDEC and AEC testing are more related to the flat bottom portion of the curve.
Calculating power converter reliability is complex, with many different combinations of components and topologies. When GaN is added into the mix, things get more challenging for several reasons:
- Performing accelerated lifetime testing can cause failures in non-GaN components.
- The correct acceleration factors for various converter topologies are not easy to identify.
- From a practical perspective, a very large (and expensive) amount of energy would be needed to run a large number of power converters for an extended period.
Testing beyond the standards
GaN-specific reliability validation is not a mature area of power electronics engineering. As a result, several suppliers of GaN HEMTs and GaN power ICs have partnered with power converter makers and users to develop qualification methodologies that parallel and expand on JEDEC and AEC-Q100. In most instances, that has resulted in establishing testing durations in excess of those called for in the standard reliability testing standards (Figure 5).
In addition to increasing the duration of the testing relative to industry standards, the number of parts being tested can be increased. AEC-Q requires the testing of three lots with 77 devices in each lot. The devices pass if there are zero failures over all the lots (231 devices). If the number of devices being tested is increased, the sensitivity of the testing also increases. If the testing takes place over a period of time, it can also provide information about the stability of the production process. One manufacturer uses 1000 hours of HTRB testing over 2000 parts, taken from the production line in lots of 50 over a period of 12 months.
The reliability of GaN HEMTs is not in question. However, due to the differences in GaN material physics and GaN device structures compared with Si devices, new ways are being developed to quantify GaN reliability. Currently, JEDEC only provides guidelines for testing and measuring the reliability of GaN devices. Several GaN makers have partnered with power converter makers and users to address user concerns. They use the ACE-Q100 standards for Si devices as a starting point. Still, testing beyond those requirements, including longer testing periods and larger lots of DUTs, accelerates the quantitative understanding of GaN reliability.
Achieving GaN Products With Lifetime Reliability, Texas Instruments
eGaN® FET Reliability, EPC
GaN-based power devices: Physics, reliability, and perspectives, Journal of Applied Physics
GaN Semiconductors Qualification and Reliability a Customer Collaborative Approach, GaN Systems
High Voltage GaN Switch Reliability, Transphorm
Reliability and qualification of CoolGaN™, Infineon
Systematic Approach to GaN Power IC Reliability, Navitas Semiconductor