There are concepts and terms in basic analog circuits which may not be familiar to designers who work primarily with digital circuits. Yet digital circuits are really specialized versions of analog ones, so these “old” analog principles play a large although somewhat invisible role. Part 1 of this FAQ discusses DC load-line basics, while Part 2 explains the use of a load line when using a transistor to linearly amplify AC signals.
Q: What is a load line?
A: The load line is a straight line which is used to locate the optimum biasing or operating point of a nonlinear device – usually a bipolar transistor or FET – in a given situation.
Q: Is the load line a new tool? Why isn’t it better known?
A: The load line is actually quite old and was developed in the early days of vacuum tubes. Its value in determining optimum point carried on to transistor-based circuits. Now, load-line analysis and positioning are often buried within an IC.
Q: But we rarely use discrete transistors these days, so why should I care about the load line?
A: First, although you may not be using a discrete transistor, the ICs you do use are built from these transistors, so the load line is still an important design factor. Second, there are many applications which are easily satisfied with basic, low-cost transistors such as the classic 2N2222 or 2N3904, which are available from dozens of vendors in many package styles. Applications for such a basic single-transistor functions are simple low-end speaker amplifiers, or driving relays and latches, as two examples.
Q: What’s the difference between the DC and AC load lines?
A: The DC (static) load line identifies the optimal point for biasing and operating a nonlinear device such as a transistor. The AC (dynamic) load line shows how varying the input to the device performing a basic function such as amplification affects and even limits performance.
Q: What does a load line look like?
A: Before you can have a load line, you need the characteristic voltage versus current graphs in one or more of the device’s standard topologies. Let’s use a basic transistor as the example in a common-emitter (CE) configuration, Figure 1, with a set of curves, Figure 2.
Q: Before we get to the load line, how is that set of curves generated?
A: You can generate them in a simple test set-up, by manually setting the base current and measuring the collector current and collector-emitter voltage. Of course, this task can be automated using an oscilloscope-like unit called a curve tracer, Figure 3, which runs the device of interest through the sequence with user-specified max/min parameter settings and load-resistor values. These curve-tracing units are available for devices ranging from small-signal transistors to high-power MOSFETs and IGBTs.
Q: What’s the next step in creating the graph?
A: The next step is to superimpose the load line on the curves, Figure 4, after determining the end-points of the load line at both axes.
Q: How is this done?
A: By Kirchhoff’s Law,
VCE = VCC – (IC × RC) where VCE is the collector-emitter voltage, VCC is the supply voltage, Ic is the collector current, and RC is the collector load resistor.
To determine point A, the collector current is maximum when collector-emitter voltage VCE = 0, and is equal to VCC/RC. Using the above equation and some simple manipulation gives the maximum value of VCE. To determine B, when the collector current IC = 0, the collector-emitter voltage is at its maximum and will be equal to the VCC. Again using the equation, we have VCE = VCC, for point B.
The collector current IC and the collector-emitter voltage VCE must always lie on the load line, and they depend only on the VCC and RC values. The DC load line is a graph that represents all the possible combinations of IC and VCE for a given amplifier. For every possible value of IC, and amplifier will have a corresponding value of VCE.
Q: What does this load-line superposition indicate?
A: First, it tells you the saturation point, the point beyond which the transistor cannot deliver any more current and thus gain. It also tells you the cutoff point, where the transistor has blocked all current flow. The load line intersects the various curves at what is called an operating point, sometimes called a quiescent point, in the center of the active linear-performance region between saturation and cutoff. Note that there are many such operating points, so the design challenge is to choose that point which assures that the transistor stays in the active region as any AC signal to be amplified is imposed on the input to be amplified.
Part 2 of this FAQ will look at how the DC load line and quiescent point apply to AC amplification performance.
References
- “What are amplifier classes and their relation to power efficiency (Part 1)?”
- “Solenoids and relays, Part 1”
- “Solenoids and relays, Part 2”
- “Impedance matching and the Smith chart, Part 1”
- “Impedance matching and the Smith Chart, Part 2”
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