Power factor and Power Factor Correction, Pt 2

Part 1 of this FAQ discussed power factor and the issues associated with power factors which are not unity, and briefly mentioned power factor correction (PFC). This FAQ explores PFC in more detail.

Q: What is PFC?

A: PFC is an adjustment of a load’s front-end “appearance” so it presents a resistive-like load to the source, thus resulting in a PF closer to unity. How close to unity it needs to be is a function of the PFC design and the desired objective, as governed by regulatory mandates.

Q: What is driving the need for PFC?

A: In addition to saving power, as a non-unity PF represents wasted power to some degree, PFC is needed to reduce the harmonics generated by an AC line by loads with non-unity PF. The further from one and closer to zero that the PF is, the worse these harmonics and line distortion will be.

Q: What are some of the regulatory mandates?

A: Due to the concern about the power waste and effects of harmonic generation that result from non-unity PFs, various regulatory standards have been established which define the allowable PF for different power levels and devices. The most important such standard is IEC-61000-3-2, “Limits for harmonic current emissions (equipment input current ≤16 A per phase)”.

This standard divides the loads into four classes (A, B, C, D) covering a diverse range of products including home appliances, home lighting, power tools, welding equipment, and much more, and at various power levels. This 2004 standard not only called out limits but also set up a schedule for tightening those limits over the succeeding years.

Q: What is the difference between PFC and harmonic reduction?

A: A specific harmonic-distortion pattern and harmonic values do not correspond directly to a given PF value, as different load-circuit inputs may produce different harmonic patterns yet have the same PF, and vice versa. The controlling standard IEC-61000-3-2 actually defines maximum levels of these harmonics out to the 40^th harmonic of the AC-line frequency, Figure 1 and Figure 2.

Fig 2: The frequency spectrum shows the harmonic components of the waveform of Figure 1 out to the 40th harmonic; the regulatory PFC standard places a great deal of emphasis on minimizing these harmonics. (Source: ON Semiconductor)

Fig 1: This is a typical waveform at the input of a switching power supply, with significant distortion despite the minimal phase difference between current and voltage. (Source: ON Semiconductor)

Q: Where is the PFC function physically implemented?

A: Before PFC became a major design and regulatory issue, it was generally installed at the power substation or the local site. For example, a factory with many motors in fixed locations might have a switchgear room with PFC-related components, usually capacitors which where shunted in line with the loads (motors). The capacitor array could be fixed or adjustable depending how many motors and their power ratings.

Since the new regulations focus on the individual end-product loads, such as switching-power supplies in home computers or video screens, the PFC is instead implemented within the end-product itself. This adds somewhat to the cost, but makes the PFC independent of where the unit is used, and does not limit the flexibility of moving it to another location.

Q: How can PFC be implemented?

A: There are two basic ways to provide PFC and harmonic reduction. The older method is the passive approach, using relatively large capacitors or inductors at the load to push the power factor towards unity and compensate for the unacceptable value. In contrast, the active approach uses an application- specific PFC IC, plus a few associated components such as small passives and MOSFETs, to shape the input current to match the input voltage waveform phase, Figure 3.

Fig 3: In an active-PFC correction approach, an application-specific IC and its support components are placed between the AC/DC rectifier bridge (or other rectifier) acting as a “pre-converter” and the bulk of the converter circuitry. (Source: ON Semiconductor)

Q: What are the passive versus active PFC tradeoffs?

A: As in most engineering situations, there is no single answer that is always correct, as it depends on cost, space, weight, performance required, and, of course, power level, Figure 4. In general, the passive approach is challenging to implement at higher-power levels as the required components get larger and costlier. Another potential disadvantage of passive PFC is that it must be designed for a specific line voltage (115 vs 230 VAC) and so the same set of passive components cannot be used in a worldwide design. However, there are cases where a one or a few passive components can solve the problem in a cost and design-effective way, as when a single large inductor can reduce the peaks of the current sufficiently and spread the current peaks out well enough to meet the regulations.

Fig 4: Comparison of the harmonic spectrum for a representative 250-W switching converter versus the IEC standard without PFC, with passive PFC, and with active PFC shows that the passive method here just barely meets the requirements are harmonic #3. (Source: ON Semiconductor)

Note that the passive approach is inherently “static” and cannot adapt to load changes or meet ever-more stringent PFC mandates. Increasingly, the dominant trend has been to use the active approach, and tailor it to the specific needs of the end product, A properly designed active circuit (the IC and support components) can bring PF close to unity, while the cost of this approach has dramatically dropped due to highly integrated ICs and the high product volumes that are a consequence of the regulatory mandates. Further, vendors of these active PFC ICs almost always provide validated reference designs which greatly ease the design-in challenge that initially slowed down the adoption of the active approach.

References