Many of the problems facing PCB designers today are related to power supply noise. There are guidelines that can be used to solve simple issues, but, for more complex issues it is essential to understand and consider all the parameters which will help in providing an optimal and clean solution.
This technical brief describes the procedure used at IDT to analyze the power supply noise rejection (PSNR) for its devices. PSNR is a measurement of how well a circuit rejects noise from various frequencies which get coupled into the power supply. In high speed analog and digital circuitry, power supply pins are vulnerable to random noise. Also, most designs use linear voltage regulators or switching voltage regulators as the power supply for ICs. Linear regulators will almost always get an input voltage from a switching DC/DC converter. Therefore, power supply noises in a design typically come from the switching noise of the power supply and coupling from other high-frequency sections of the circuit board.
Topology of a power supply filter
Figure 1 is a simplified 3-component power supply filtering circuit that is recommended for a power rail. It consists of a 0.1μF capacitor (C1), a ferrite bead (FB1) and a 10μF capacitor (C2). While C1, FB1 and C2 are for the power rail, C3 is used for each power pin supplied by this rail. If a power rail supplies multiple power pins, each power pin will have a 0.1μF capacitor for decoupling.
Figure 1. Topology of the Power Supply Filter
The ferrite bead above is any surface-mount bead with sufficient current rating for the circuits supplied.
Frequency Response of the Noise Filtering Circuit
The attenuation capability demonstrated by the circuit shown in figure 1 can be understood by studying its frequency response. In the following sections of this technical brief, frequency response of the circuit is plotted by sweeping C1, C2 and C3, respectively:
Figure 2: Sweeping C1 while keeping C2 = 10μF, C3 = 0.1μF – Optimal value for C1 is 0.1μF
Figure 3: Sweeping C2 while keeping C1 = 0.1μF, C3 = 0.1μF – Optimal value for C2 is 10μF
Figure 4: Sweeping C3 while keeping C1 = 0.1μF, C2 = 10μF – Optimal value for C3 is 0.1μF
Figure 2. Sweeping C1 while keeping C2 = 10μF, C3 = 0.1μF
Figure 3. Sweeping C2 while keeping C1 = 0.1μF, C3 = 0.1μF
Figure 4. Sweeping C3 while keeping C1 = 0.1μF, C2 = 10μF
Measuring Power Supply Noise Rejection
PSNR is measured by injecting a sinusoidal signal of a known amplitude and frequency onto the various power supply pins of the device under test (DUT). Many of the devices in the IDT Timing portfolio contain multiple power supply pins. The two pins of interest are the core power pin and the analog power pin. The core power pin primarily supplies voltage to all PLL peripherals while the analog power pin supplies the voltage to the PLL. Each power pin should be analyzed independently, and noise should be applied to one power pin at a time.2
The technique used for applying the injected frequency into the device supply uses an inductor which presents a high AC impedance back to the supply. A signal from a generator is then injected through a capacitor configured as shown in figure 5. Both the input and output should be monitored with an oscilloscope and spectrum analyzer. The oscilloscope is used to monitor the signal amplitude while the spectrum analyzer is used to measure the deterministic jitter.
Figure 5. Configuration Used to Measure PSNR
In order to analyze the performance of the device, all external bypass and decoupling capacitors are initially removed. A 50mV signal is swept from a start to a stop frequency. In this case, a 1 kHz to 50 MHz sweep range is used, which covers the majority of noise frequencies in typical applications. Table 1 summarizes the configuration parameters.
Results of three PSNR tests are shown in figure 6. First, the device was swept without any decoupling or bypass capacitors. Notice, the deterministic jitter peaked at approximately 400 kHz. Next, a 0.1μf bypass capacitor was added and the noise decreased significantly. Lastly, in addition to the 0.1μf, a 10 μf capacitor was added and majority of the noise is filtered.
Figure 6. Deterministic Jitter Versus Noise Frequency
Figure 7. Noise Rejection Comparison: 0.1μF Capacitor Only vs Filtering Circuit by Figure 1
As demonstrated by these measurements, the combination of a 0.1μf and 10μf capacitor will attenuate the majority of noise generated by a switching power supply. The addition of a ferrite bead will further attenuate noise in the 100kHz to 600kHz range and is recommended. Figure 7 provides a comparison between a 0.1μf-only filter and a filter comprised of all the elements shown in figure 1, including the ferrite bead.
This technical brief illustrates the effectiveness of a simple power supply noise rejection topology consisting of two capacitors and a ferrite bead. By sweeping the values of the capacitors, a noise-filtering circuit with recommended component values is provided in Figure 1. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added to address these specific noise components. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices.
Integrated Device Technology, Inc.