Most of voltage regulators are still using discrete solutions like SO8-FL 5 x 6 mm2 package. With advancement of Si technology and packaging, MOSFET can achieve a switching transition of less than 10nS, which is equivalent to di/dt of more than 1A/nS New PowerPhase packages enable faster switching by minimizing package parasitic inductances. While the old solutions of using SO8-FL are less efficiency new integrated packages, layout requirements were less critical and switching frequency limited by the package parasitic inductance. This application note points out some of the power MOSFET application concerns in modern high power density voltage regulator. The following topics will be discussed:
- SO8-FL vs PowerPhase
- Power Loop
- Decoupling Capacitor Placement
PowerPhase Application Issues
- Phase Node Overshoot
- Low Side Off-State Gate Bounce
- High Side Kelvin Connection
- Low Side Gate Resistor
- Different High Side Driver Connections
Structural Differences in SO8-FL and PowerPhase packages
SO8-FL and PowerPhase packages are 5 x 6 mm2. Traditional SO8-FL package has MOSFET’s drain connection attached to the lead Fig1frame and source clip bonded (Figure 1). PowerPhase is dual dies device in a half-bridge configuration. Low side die is flipped with source attached to the lead frame and high side die has a kelvin source connection (Figure 2).
In synchronous buck converter, two MOSFET devices form a half-bridge configuration. SO-8FL solution (Figure 3) has a minimal of 1nH total package inductance from two interconnect clip parasitic Fig3inductances. PowerPhase solution’s inductance is reduced by half (Figure 4). PowerPhase also reduced switching time by utilizing high side kelvin connection which bypassed clip inductance in driver loop .
Minimize Power Loop
Due to the kelvin connection, drain current transition speed di/dt has increased. Phase node voltage overshoot can be very severe. During the high side switching transitions, the current is provided by the decoupling capacitor. Parasitic power loop inductance and low side output capacitance (Figure 5) forms a resonant circuit causing phase node ringings and power losses. The power loop is the high current di/dt path (Figure 6). Total power loop inductance is formed Fig5by the package and the layout inductance between the input decoupling capacitor. One way to reduce ringing energy, power loop inductance needs to be minimized.
Input Decoupling Capacitor Placement
Due to the close proximity of input voltage pin and ground pin on the PowerPhase footprint , minimal power loop inductance (PL1 in Figure 7) can be achieved by placing decoupling capacitor next to pin 4. The next best placements will be either placing directly below (PL3 in Figure 7) or in line with the PowerPhase (PL2 in Figure 7). Both placements utilized inner PCB layers for magnetic field cancellation. On a typical 4-layer 40 mil board thickness with 2nd Fig7layer as ground plane, power loop inductance for placement PL1 is approximated to be 1.3nH including package contribution. Placement PL2 and PL3 is approximated to be 1.4nH.
Recommended PowerPhase Layout
The recommended layout show in figure 8’s goal is to separate high current path from the signal path. In Figure 9, red shaded high current path creates induced noise voltage from parasitic inductances. By placing input decoupling capacitance and gate signals on opposite sides, their interferences can be minimized. If possible, place driver IC close to G2 pin for minimal low side gate bounce. Thermal vias are most effective in reduce junction temperature when placed underneath the package. Important layout rules are summarized:
- Minimize power loop area
- Input decoupling capacitor placement
- Use S1 pin as high side driver return
- Thermal vias underneath footprint
- Minimize controller signal and power loop overlap
Low inductance probing technique is required for assessing over voltage risk. In figure 10a, Red stars indicate recommended probe locations for VGS and VDS measurements. A common mistake in probing is referencing to the wrong ground point (black dots). For example, referencing all probes to input capacitor ground will add LPCB·di/dt noise into the measurement.
Two low side gate waveforms, VGS, were captured with different ground references. There is a major difference in the initial gate bounce (Figure 10b). With correct probing of PowerPhase VGS, LGATE, initial gate bounce negative due to board inductance di/dt. LGATE2 waveform is a distortion of true VGS with parasitic inductance noise. LGATE2 waveform is similar to package with source clip inductance. High gate inductance from routing will minimize the initial negative gate bounce.
This fast switching PowerPhase packages required best layout practices. In multiphase voltage regulator with discrete MOSFETs, space and orientation constraints produce suboptimal layout designs.
Phase Node Overshoot
Phase node voltage should not exceed low side MOSFET’s drain-to-source breakdown voltage. Probing the phase node voltage should be as close to the low side drain-source as possible (refer to Figure 10a). Phase node ringing is caused by the low side reverse recovery Fig12current in the resonant tank formed by the total power loop inductance and the low side output capacitance (Figure 11). Snubber or high side boost resistor can be added to reduce phase node overshoot.
Low Side Off-State Gate Bounce
There are two contributions to the gate bounce. Current injection from CGD due to phase node dv/dt and resonant tank ring due to source inductance di/dt. During the high side turn-on rising phase node voltage cause a dv/dt across the CGD of the low side MOSFET, current flow through the CGD and splits between gate resistor and CGS (Figure 12a). The worst case for dv/dt will be a large gate resistance causing most CGD current to be charging the CGS. Induced gate voltage from dv/dt is shown below:
Low side source, board inductance and gate capacitance, CGS, formed a resonant tank and with reverse recovery current produce another gate bounce contribution (Figure 12b). The first positive peak voltage across the parasitic inductance caused the low side gate-source voltage to be more negative (Figure 11). The following negative peak voltage causes the low side gate-source voltage to go positive and potential turning on the low side MOSFET. Under the worst case small Rg condition for di/dt, energy in the source, LS, and board inductance, LPCB, oscillate and transfer energy between CGS with little damping. Long gate routing (high gate inductance, LG) creates additional gate oscillation at a lower frequency.
S1 pin – High Side Kelvin Connection
For high side MOSFET, a dedicated gate driver return pin (S1 pin) increase switching speed (Figure 13) and efficiency. In discrete solutions, this kelvin source implementation is needed for achieving highest efficiency. These low inductance packages increase di/dt Fig15transition tremendously. The risks of faster switching speed without improved layouts are increase voltage overshoot and potential shoot-through.
Adding 1Ω Low Side Gate Resistor
Due to the high side kelvin connection, very fast switching transitions could cause shoot-through. With the increase in speed and reduce in MOSFET capacitance, synchronous MOSFET is very susceptible to noise injection from high di/dt. A small low side gate resistor can be added to increase damping in low side MOSFET gate driver loop. This additional small gate resistor will have little impact on switching loss of synchronous low side MOSFET, but a huge increase in di/dt shoot-through immunity (Figure 14).
In multiphase controller using discrete MOSFETs, gate routing inductances, LG, and board inductances, LPCB, are unavoidable (Figure 15). During the high side MOSFET turn-on, drain current di/dt will create a ground bounce with respect to the driver IC ground reference. The worst gate bounce will occur for phase that is the furthest away from the driver IC. Ground bounce signal filtering can be increased by increasing total gate resistance, RG.
Different High Side Driver Connections
There are two phase node connections, S1 and SW, available on PowerPhase package. S1 and SW pin are internally connected by a metal clip. Although the resistance of the clip is only 0.3mΩ, its inductance is 0.5nH. During the turn-on and turn-off transitions, drain current di/dt (>1A/ns) can induced a few volts across the clip. These induced voltages slow down switching transitions resulting in lower efficiency but yield a smaller magnitude of phase node ringing. It is common for users to priorities ease of routing by connecting high side driver signal from SW pin. Four different possible high side driver connections are shown in Figure 16. Their impacts on performance are summarized in Table 1. In Figure 17, high side driver turn-on path is indicated by the green stripe region and turn-off path in red shaded region. The recommended high side driver connection in Figure 17a bypassed the internal clip impedance.