What is new in UCIe 3.0?

Universal Chiplet Interconnect Express (UCIe) 3.0 is focused on increased bandwidth, improved power efficiency, and enhanced system-level management for next-generation chiplet-based designs. It’s designed to support artificial intelligence and high-performance computing while maintaining backward compatibility with UCIe 2.0 and 1.0.

UCIe 3.0 continues to support 3D packaging. It doubles the bandwidth of UCIe 2.0 and supports data rates up to 64 GT/s to meet the requirements of data-intensive applications.

Higher speed and improved power efficiency are key advances in the latest iteration. These features include runtime recalibration for dynamic link tuning and priority sideband packets that support low latency.

The L2 state is focused on delivering deep power savings by powering off the interconnect, except for auxiliary functions. It prioritizes power savings over minimum wake-up latency.

The sideband channel reach has been extended to 100 mm to support increased scalability for flexible multi-chip configurations. Raw mode provides a flexible and low-latency mechanism for transmitting data between chiplets without relying on the full functionality of the die-to-die adapter layer. This mode is particularly useful for applications requiring uninterrupted data flow or when connecting to specific types of dies that handle their own protocol stacks.

The UCIe design for excellence (DFx) architecture is a holistic approach that considers manufacturability, assembly, testability, cost-effectiveness, reliability, and quality over the entire product lifecycle.

DFx supports testing, telemetry, and debugging to facilitate vendor-agnostic chiplet interoperability and unified system in package (SiP) management. It enables better monitoring, analysis, and the use of more sophisticated redundancy and fault recovery strategies.

Fast throttle and emergency shutdown enhance system reliability and stability in complex designs. Fast throttle provides a quick and efficient way for the system to reduce the operating speed or power consumption. Emergency shutdown is designed to initiate an immediate and safe shutdown of affected chiplets or the entire system in response to critical failures or hazards.

A summary of key performance metrics for UCI2 3.0 is detailed in Table 1.

Table 1. Selected performance metrics for UCIe 3.0. (Table: The Next Platform)

Higher reliability

UCIe 3.0 adds enhancements to support better redundancy and higher reliability for high-performance chiplet interfaces, including improved recalibration capabilities and addressing many of the 3D packaging limitations of 2.0

Improved recalibration capabilities allow chiplet links to dynamically adapt to environmental variations and drive in real time. That improves signal integrity without the need for large design margins (guard banding). It can be useful for simultaneously maximizing interconnect reliability and power efficiency at high data rates.

UCIe 3.0 expands on the foundation of 3D packaging support established in UCIe 2.0, addressing many of the 3D packaging limitations of 2.0. That’s particularly true in the areas of testing and debugging, improved interoperability, and support for more advanced packaging technologies that are crucial for fully realizing the potential of 3D packaging with chiplets.

Improved redundancy

Two approaches are outlined for improved redundancy. For packages using µbumps, redundant lanes can be available. In those packages, UCIe 3.0 includes two redundant lanes for every 32 data lanes, allowing for the replacement of failing signal interconnects between chiplets. Faulty lanes can be substituted for during manufacturing or in-field operation, improving assembly yield and addressing potential wear-out failures.

For standard flip-chip packaging using controlled collapse chip connection (C4) bumps or copper pillars (CuPillar) with high yields, UCIe 3.0 supports a graceful degradation approach. If a lane failure occurs, the system can reduce the operational width of a module, for instance, from 16 lanes to 8.

Figure 1. The faster throttle and emergency shutdown mechanisms in UCIe 3.0 improve thermal management performance. (Image: ServeTheHome)

UCIe uses source repair muxing (SRM) to manage interconnect defects. SRM uses muxes to allow multiple physical fault signals (SFS) to connect to each interconnect source (IS). In the case of an interconnect failure, SRM shifts PFS to an alternative IS and bypasses the fault.

UCIe 3.0 added a common dedicated open-drain bidirectional pin that connects all chiplets in a common thermal zone. Any combination of chiplets can assert fast throttle thermal management. When asserted, all chiplets in the zone throttle to a pre-established level and at a defined rate (Figure 1).

Summary

UCIe 3.0 provides a significant advance in performance compared with version 2.0. It will enable designers to more fully realize the performance potential of chiplets in 3D packages for advanced applications like AI and HPC. In addition to higher performance, it supports improved interconnect redundancy and reliability, plus it has better thermal management tools.