What is the IEEE 1801-2024 Unified Power Format 4.0 standard?

IEEE Unified Power Format (UPF) 4.0 is a standard specification language that defines the low-power architecture of low-power ASICs. It’s designed to streamline integration throughout the design, verification, and implementation process, with a focus on power intent for energy-aware electronic system design.

UPF is built using the Tool Command Language (TCL) and complements hardware description languages such as SystemVerilog and VHDL. It enables designers to specify essential power intent elements like power domains, power states, power transitions, and other factors needed to maximize the performance of low-power ASICs.

As a standardized language and framework, UPF supports portability and consistent performance across various design tools throughout the EDA tool flow. UPF power intent files are structured for use during design, verification, and implementation (Figure 1).

Figure 1. Example of an EDA workflow showing the insertion of the power intent files. (Image: Defacto Technologies)

Key elements

The key elements of IEEE 1801 begin with the power supply network that defines the power architecture of the chip and how power is delivered to the various power domains and logic cells. Next are power domains, which are groupings of logic blocks, memory, and other elements that are treated as a single unit for power management purposes.

Three possible states define power domain operation. The normal powered operating state is a low-power state called standby, idle, or drowsy, where the domain is temporarily inactive but retains its state. The other states are off or sleep, where the domain is powered off and may lose its state.

Power domains are a key concept for defining power intent and managing overall power consumption through functions such as level shifters, isolation, and retention cells. UPF can define the locations and specifications of level shifters for connecting different voltage domains, ensuring that signals from one voltage domain can be correctly interpreted by another domain.

UPF supports insertion of isolation cells to prevent undesired power leakage between power domains and retention cells or retention registers that save the state of a power domain when power is removed.

Macros are used to capture the power intent and characteristics of a domain. They support simplified integration and IP reuse. They also provide a detailed description of the domain operating states required for design verification under various power conditions (Figure 2).

Figure 2. Key elements of the IEEE 1801 UPF standard. (Image: Cadence)

New features in 4.0

The UPF 4.0 release introduced several enhancements and new features to improve low-power design and verification. Three key enhancements are improved value conversion methods (VCMs) that replace value conversion tables (VCTs), enhanced retention modeling, and refinable macros.

Compared to VCTs, VCMs offer better performance in analog/mixed-signal designs and provide a richer and more flexible method for translating between UPF supply nets and HDL. UPF 4.0 combines VCMs with tunneling to connect supplies to various HDL types, providing a more consistent power intent representation throughout the design and verification process.

Enhanced retention modeling includes more control over save/restore conditions, including the ability to handle more complex clock, setup, and retention relationships. The finer control over save/restore conditions and the ability to consider the effects of asynchronous signals on retention cells support more accurate modeling of power states.

The new version introduced refinable macros that simplify IP reuse and design optimizations. Refinable macros can have variable terminal boundaries, tool-enforced safety with non-intrusive power intent updates, enabling system-level optimization during the design process. They also support bottom-up design verification, simplifying the integration of IP blocks.

Other enhancements in 4.0 include:

Improved successive refinement, making it more effective for managing design updates.
Clarification of precedence rules for resolving conflicting power intent specifications, resulting in more consistent and predictable behavior.
Virtual supplies enable modeling of supplies that are not physically connected, simplifying power state definitions.
The UPF library has been enhanced with pre-defined power intent elements designed for reuse, which speeds up the design process.

Summary

IEEE UPF 4.0 provides a standardized way to describe and manage power-related information in low-power IC designs and enables the development of power-aware electronics. The latest version supports better collaboration across different design phases and tools, leading to more efficient, accurate, and predictable low-power designs.