Low power design is a system using a collection of techniques and methodologies for the purpose of optimizing battery life and reducing the overall power dissipation of the system. To optimize the power, there are many low-power techniques that depend on the level of the design selected, ranging from semiconductor technology to higher levels of abstraction. These abstraction levels are classified as a system, algorithm, architecture, circuit, and process levels which we will discuss further in the article, and we will examine some of the information related to reducing power consumption on embedded systems. Then in a future article, we will discuss the features of the microcontroller-based low-power system and how you can use them to extend your battery life.
Before we go any further, we should know these terms:
Current is a measure of the amount of electrical charge transferred per unit of time through a closed circuit. The standard unit is amperes, which is defined as coulombs (a unit of charge) per second.
Power (electric power) (P) is the rate at which work is done or energy is transformed into an electrical circuit.
P = VI
Where V is the potential difference in the circuit and I is the electric current through the electric circuit
Energy is the ability to do work. If the power is constant over the time interval then the energy can be expressed simply as:
E = Pt
If power consumption is constant, energy consumption will be power * time during which power is consumed. Power consumption reduction will only save energy if the time required to complete the task does not increase.
Let us understand low power embedded systems by doing an experiment with LED brightness. Our aim here is to demonstrate how we can drive load on low power using an MCU.
Here we have used an Arduino to control the brightness of the LED. Arduino provides PWM (pulse width modulation) that can periodically output HIGH and LOW. The PWM function, periodically switching between HIGH and LOW at a specified rate, can be used to adjust the LED brightness.
To create a PWM signal, we use the function analogWrite(x, y), where x is the digital pin and y is a value for the “duty cycle,” between “0 and 255” where 0 indicates 0% duty cycle and 255 indicates 100% duty cycle which means when the PWM ratio reaches 255, it is decreased until it reaches 0 to darken the LED gradually.
The duty cycle is the ratio of time a load or circuit is ON compared to the time the load or circuit is OFF. A 60% duty cycle is a signal that is ON 60% of the time and OFF 40%.
Done when the PWM ratio is 10 and duty cycle is 4%.
The low brightness of the LED (10 %) uses less drive current which means less power is consumed. With 100mA of battery with a load of 0.1mA, the run time will be 1000 hours.
Done when the PWM ratio is 150 and duty cycle is 58%.
The half brightness of the LED (58 %) uses the half drive current which means half power is consumed. With 100mA of battery with a load of 1.85mA, the run time will be 54 hours.
Done when the PWM ratio is 255 and duty cycle is 100%.
The full brightness of the LED (100 %) uses the full drive current which means more power is consumed. With 100mA of battery with a load of 3.16mA, the run time will be 31 hours.
The current is proportional to the LED brightness. So, the current is less if the LED’s brightness is less which implies that low power consumption will equal low energy consumption.
Why do we need low power design?
Embedded systems need to be energy efficient during operation to ensure a long battery lifetime, reduce utility power consumption, and prevent excess heat generation. The longer battery life of a product can also lead to lower maintenance costs, as costly visits to replace batteries occurs less frequently. Additionally, portable devices such as cellular phones, gaming consoles, and battery-powered electronic systems demand microelectronic circuits designed with ultra-low power dissipation. For example, metering solutions like automatic meter reading (AMR) require longer battery life and portability as they need to be fixed on each and every meter. They should run about 8- 10 years after the installation.
Levels of power optimization
The low power design of any system is a combination of optimized manufacturer, software, and hardware. In these combinations power reduction can be implemented at different levels of design abstraction: system, architecture, algorithms, circuit, and the process level. The most efficient design decisions derive from choosing and optimizing architectures and algorithms at these levels. Let’s discuss these levels briefly on which energy reduction can be incorporated:
System level: This level includes the power optimization techniques which can be done at the time of manufacturing of ICs and also at the hardware level. For example, design partitioning is the practice of dividing a system on chip (SoC) into small blocks which is done on the manufacturer’s side. This allows users to efficiently manage semiconductor designs as a related set of functional blocks. Semiconductor designs are most efficiently managed as related sets of functional blocks.
Algorithmic level: In this technique, the number of operations that require larger power is reduced and basically part of the software; this approach reduces the number of operations and hence reduces the number of hardware resources. For example, most DSP (digital signal processing) algorithms involve several multiplication operations. Multiplication is the most power-consuming operation in such algorithms and can be replaced by shift-add (this method adds the multiplicand X to itself Y times, where Y denotes the multiplier) operations to reduce power.
Architectural level: Architecture level measures include smart power management of various system blocks, utilization of pipelining and parallelism, design of bus structures, and voltage scaling. At this level, the power reduction can be done on both the hardware and software side. For example, energy consumption in CMOS circuitry is proportional to capacitance. While designing the PCB we can minimize the bus length by optimal module placement which will reduce the capacitance.
Logic/circuit design level: This level includes the power optimization techniques which can be done at the time of manufacturing of ICs, hardware, and the software side as well. For example, transistor sizing is the process of reducing or increasing the channel width of the transistor at the time of manufacturing. The smaller the transistors, the more transistors can fit on a chip, and the faster and more efficient the processor can be. Another example is to use a custom design at the hardware side in which components in a circuit used are more static than dynamic.
Process level: This level includes the power optimization techniques which can be done only on the hardware side of the system. For example, multi-supply voltages are being used in different functional blocks of the core for saving power. Another example, reducing a supply voltage from 5.0 to 3.3 volts (a 44% reduction) reduces power consumption by about 56%.
**We will discuss these in detail in a future article.
Power modeling is a technique or procedure to study the power generated, lost, and distributed in a system. It helps in recording past data of power flow and preparing future plans and system design.
In power modeling the total power dissipation (PT) can broadly be divided into the following:
Static power dissipation (PS): Power consumed during a standby mode (when the microcontroller is in sleep mode but LDO (low drop out) is active and consumes power).
Dynamic power dissipation (PD): Power dissipation during a signal switching at the cell input during and discharging of the capacitances in the circuit. Switched capacitance is the primary source of dynamic power consumption and arises from the charging and discharging of capacitors at the outputs of circuits.
Short circuit power dissipation (PSC): The secondary source of dynamic power consumption where power is dissipated by an instantaneous short-circuit connection between the supply voltage and the ground at the time the gate switches state which can cause dissipation of more than 20% of the total power.
PT = PS + PD + PSC
Low power embedded system applications
These include the following:
- Low maintenance Devices
- Digital wristwatches
- Fitness tracker
- Interactive Kiosks
- Mobile Phones
- Unattended Internet-of-Things (IoT) systems